The present invention relates to an LSI and a wiring-substrate circuit. More particularly, the present invention relates to a method used for verifying a designed circuit in order to detect and correct electrical characteristics of circuit components composing the designed circuit.
As has been commonly known, there are voltage drops referred to as so-called IR drops inside an LSI or a wiring-substrate circuit from the level of a voltage appearing at a power-supply pin of the LSI or the wiring-substrate circuit due to an effect of an operation current flowing during an operation of the LSI or the wiring-substrate circuit.
There has been proposed a variety of techniques for analyzing the phenomenon of a drop in power-supply voltage. In accordance with the techniques, however, a result of analysis is revealed by merely displaying the magnitude of a voltage drop along a wire, at a via hole or a cell terminal, or merely displaying a current density. There has not been reported a technique whereby a result of analysis identifies the location of a wire abnormality so as to allow the abnormality to be corrected with ease.
It is thus an object of the present invention addressing the problems described above to provide a designed-circuit-verifying method for verifying a designed circuit with ease at a designed stage of the circuit or an LSI containing the circuit.
To solve the problems described above, according to a first aspect of the present invention, there is provided a designed-circuit-verifying method including: a process of designing a predetermined circuit; a process of simulating reference data representing electrical characteristics of circuit components composing the designed circuit; and a process of detecting electrical characteristics of the circuit components and comparing the detected electrical characteristics with the reference data.
The designed-circuit-verifying method is also referred to hereafter as an invention verification method.
In accordance with the invention verification method, for a circuit component of a designed circuit, electrical characteristics of the circuit component are detected by simulation and compared with reference data. Thus, an electrical characteristic different from the reference data or the location of a circuit component having such an electrical characteristic can be identified with ease. On the basis of the result of comparison, it is possible to show an electrical characteristic different from the reference data on a display of a circuit component exhibiting the electrical characteristic. By showing such an electrical characteristic on a display of the circuit component, the designed circuit can be corrected with ease. As a result, it is possible to provide a method of verifying a designed circuit to increase a design efficiency.
It is desirable to provide an invention verification method for comparing an electrical characteristic of each circuit component employed in a designed circuit with reference data and identifying an electrical component to be corrected on the basis of the result of comparison so as to allow the designed circuit to be corrected with ease.
It is thus desirable to further provide an invention verification method with: a process of displaying reference data representing an electrical characteristic of a circuit component employed in a designed circuit on a computer screen if necessary; a process of fetching detected data of the electrical characteristic of the circuit component; a process of comparing the fetched electrical characteristic with the reference data and forming a judgment on a result of comparison; and a process of displaying a result of the judgment on the computer screen.
In this case, it is desirable to select at least one electrical characteristic to be detected among a group of electrical characteristics including a voltage applied to a power-supply wire, a voltage drop, a power consumption, a current and a current direction, which are observable for each circuit component employed in the designed circuit.
To put it in detail, after simulation of voltage drops and others on the computer screen is ended, on the basis of comparison of an analysis result with reference data and on the basis of a judgment on a result of the comparison, detected data are fetched. For example, in addition to displays of a voltage drop along a Vdd wire, a voltage drop at a via hole, a ground bounce on a Vss wire and a ground bounce at a via hole, voltages supplied to a cell and a macro or an LSI are also displayed. In the case of a cell to which voltages Vdd and Vss are supplied, for example, a difference in electrical potential between the voltages Vdd and Vss is displayed. As an alternative, a sum of a voltage drop of the voltage Vdd and a ground bounce of the voltage Vss is displayed. The displays are graphical displays, which are colored in accordance with their values, or ASCII outputs sorted in the order of ascending/descending values.
As another example, the direction of a current flowing through a wire is displayed so as to allow the design engineer to verify that the current indeed flows in a direction intended by the engineer. In addition, in case a current flows in a direction opposite to the supposed direction, that is, in case a current flows out from a terminal of a macro or a cell instead of flowing into the terminal as expected, or flows into a terminal of a macro or a cell instead of flowing out from the terminal as expected, the display also includes a warning identifying the terminal.
As a further example, a power consumption (or a current) per unit area of a cell or a macro is computed and displayed in a color depending on the value of the power consumption (or the current) or output at a location among those arranged in an ASCII sort. A power consumption (or a current) per unit area of a cell or a macro is defined as a ratio of a power consumption (or a current) of the cell or the macro to the area of the cell or the macro.
It is desirable to select at least one electrical characteristic to be detected among a group of electrical characteristics including a current or the density of a current flowing through each connection hole of every circuit component, a current or the density of a current flowing through each wire, a current or the density of a current flowing through a multi-layer wiring substrate, a supplied voltage, a voltage drop and the location of each connection hole.
As a still further example, the display includes a warning identifying a via hole, a contact or a wire, through which almost no current is flowing or a current smaller than a specified magnitude or a current having a density smaller than a specified value is flowing. Such via holes, contacts and wires are displayed in a sorted order of typically ascending values. Portions of wires having electric potentials different from each other may be located at positions of the same planar coordinates but pertain to different layers. In case a difference in power-supply voltage drop between such wire portions is greater than a specified value, the coordinates of the positions of the wire portions are identified and a warning for creation of a via hole is issued.
The user is also allowed to determine whether or not to display such information in dependence on typically the distance between layers or the number of layers. In addition, if a signal line is sandwiched between 2 power-supply-wiring layers in a multi-layer structure, the user is allowed to select an option of displaying no warning.
The above and the other objects, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiment of the invention in conjunction with the accompanying drawings.